1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device that is used for a CMOS circuit that includes n-MOS transistors and p-MOS transistors.
Priority is claimed on Japanese Patent Application No. 2007-120317, filed Apr. 27, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
The semiconductor integrated circuit has an integration of a large number of MOS field effect transistors. The MOS field effect transistors that are integrated on the semiconductor integrated circuit are classified into n-MOS transistors and p-MOS transistors. Most of the n-MOS transistors and p-MOS transistors constitute CMOS circuits. Scaling down of the n-MOS transistors and p-MOS transistors are necessary for improving the high speed performances of the semiconductor device or the CMOS circuits and also for realizing large scale integration.
Scaling down of the n-MOS transistors and p-MOS transistors needs reduction in thickness of gate insulating films in those transistors. Reduction in thickness of the gate insulating film may raise the problem with negative bias temperature instability (hereinafter referred to as NBTI) of the p-MOS transistors, resulting in decrease of the reliability of the p-MOS transistors. NBTI is the phenomenon that a negative bias voltage (Vg<0) as a stress voltage is continuously applied to the gate electrode of the p-MOS transistor, thereby increasing the threshold voltage of the p-MOS transistor and decreasing the on-current. This phenomenon may cause malfunction of the circuits. The problem in reliability with the NBTI provides the bars to reduction in thickness of the gate insulating film of the p-MOS transistor and also to improvement in high speed performance of the CMOS circuit.
In order to countermeasure the NBTI problem, it was proposed to increase the thickness (Tox(PMOS)) of the gate insulating film of the p-MOS transistor so as to reduce the field applied to the gate insulating film of the p-MOS transistor, while unchanging the thickness (Tox(NMOS)) of the gate insulating film of the n-MOS transistor. Forming thickness-difference gate insulating films of the n-MOS transistor and the p-MOS transistor needs additional lithography process, for example, multi-oxide photo-resist process, resulting in increasing the number of manufacturing process for the semiconductor device.
FIGS. 4A through 4F are fragmentary cross sectional elevation views illustrating conventional semiconductor devices in sequential steps involved in a conventional method of manufacturing the same. FIG. 5 is a fragmentary cross sectional elevation view illustrating the conventional semiconductor device that is formed by the conventional manufacturing method shown in FIGS. 4A through 4F. The conventional semiconductor device has an n-MOS transistor and a p-MOS transistor. The n-MOS transistor has a second gate insulating film of a second thickness Tox(NMOS). The p-MOS transistor has a first gate insulating film of a first thickness Tox(PMOS). The first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS).
With reference to FIG. 4A, isolation regions 102 are selectively formed in an upper region of a silicon substrate 101, thereby defining active regions on the silicon substrate 101. A first gate insulating film 103 is formed over the active regions on the silicon substrate 101 and the isolation regions 102. The first gate insulating film 103 has a first thickness in the range of 3 nanometers to 10 nanometers.
With reference to FIG. 4B, the silicon substrate 101 has an n-MOS transistor region 104a and a p-MOS transistor region 104b. A first resist film is applied on the first gate insulating film 103. A photo-lithography process is carried out to form a first resist pattern 105 in the p-MOS transistor region 104b. The first resist pattern 105 has an opening over the n-MOS transistor region 104a. A wet etching process is carried out using the first resist pattern 105 as a mask to selectively remove the first gate insulating film 103 in the n-MOS transistor region 104a, while leaving the first gate insulating film 103 in the p-MOS transistor region 104b. The surface of the n-MOS transistor region 104a of the silicon substrate 101 is shown. The wet etching process is carried out using an HF-based etchant.
With reference to FIG. 4C, the first resist pattern 105 is removed. A thermal oxidation process is carried out to selectively form a second gate insulating film 106 on the n-MOS transistor region 104a of the silicon substrate 101. The second gate insulating film 106 has a second thickness in the range of 1 nanometer to 3 nanometers. The first gate insulating film 103 is formed in the p-MOS transistor region 104b. The second gate insulating film 106 is formed in the n-MOS transistor region 104a. The first gate insulating film 103 on the p-MOS transistor region 104b is greater in thickness than the second gate insulating film 106 on the n-MOS transistor region 104a. 
With reference to FIG. 4D, a thermal chemical vapor deposition process is carried out to form a non-doped polysilicon layer 108 over the first gate insulating film 103 on the p-MOS transistor region 104b and the second gate insulating film 106 on the n-MOS transistor region 104a. The non-doped polysilicon layer 108 has a thickness in the range of 50 nanometers to 100 nanometers.
With reference to FIG. 4E, a second photo-resist film is applied on the non-doped polysilicon layer 108. A lithography process is carried out to form a second resist pattern 111 on the non-doped polysilicon layer 108. A dry etching process is carried out using the second resist pattern 111 as a mask to selectively remove the non-doped polysilicon layer 108, thereby forming gate electrodes 110a and 110b on the second and first gate insulating films 106 and 103 in the n-MOS transistor region 104a and the p-MOS transistor region 104b. 
With reference to FIG. 4F, the second resist pattern 111 is removed from the gate electrodes 108. A first ion-implantation of n-type dopant is carried out using the gate electrode 110a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104a of the silicon substrate 101, thereby selectively forming n-doped regions in the n-MOS transistor region 104a. A second ion-implantation of p-type dopant is carried out using the gate electrode 110b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104b of the silicon substrate 101, thereby selectively forming p-doped regions in the p-MOS transistor region 104b. 
Side wall insulating films 113 are selectively formed on the side walls of the gate electrodes 110a and 10b. The side wall insulating films 113 have a thickness in the range of 5 nanometers to 20 nanometers. The side wall insulating films 113 may be made of an insulator such as oxide or nitride.
A third ion-implantation of n-type dopant is carried out using the side walls 113 and the gate electrode 110a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104a of the silicon substrate 101, thereby selectively forming n-type source and drain regions 112a and 112c of lightly doped drain structures in n-MOS transistor region 104a. The third ion-implantation is carried out at higher acceleration energy than that of the first ion-implantation so as to introduce the n-type dopant into the deeper level than the n-doped regions, thereby forming the n-type source and drain regions 112a and 112c having the n-type lightly doped drain structures.
A fourth ion-implantation of p-type dopant is carried out using the side walls 113 and the gate electrode 110b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104b of the silicon substrate 101, thereby selectively forming p-type source and drain regions 112b and 112d of lightly doped drain structures in p-MOS transistor region 104b. The fourth ion-implantation is carried out at higher acceleration energy than that of the second ion-implantation so as to introduce the p-type dopant into the deeper level than the p-doped regions, thereby forming the p-type source and drain regions 112b and 112d having the p-type lightly doped drain structures.
The gate electrode 110a in the n-MOS transistor region 104a is doped with the n-type dopant by the first and third ion-implantations. The gate electrode 110b in the p-MOS transistor region 104b is doped with the p-type dopant by the second and fourth ion-implantations.
An annealing process is carried out to activate the n-type dopant and the p-type dopant in the n-type source and drain regions 112a and 112c and the p-type source and drain regions 112b and 112d. 
With reference to FIG. 5, an inter-layer insulator 114 is formed over the first and second gate insulating films 103 and 106 and the gate electrodes 110a and 110b with the side wall insulating films 113. Contact holes are formed in the inter-layer insulator 114. The contact holes penetrate the inter-layer insulator 114. The contact holes reach the n-type source and drain regions 112a and 112c and the p-type source and drain regions 112b and 112d as well as the gate electrodes 110a and 110b. Contact plugs 115 are formed in the contact holes of the inter-layer insulator 114. The contact plugs 115 penetrate the inter-layer insulator 114. The contact plugs 115 contact the n-type source and drain regions 112a and 112c and the p-type source and drain regions 112b and 112d. The contact plugs 115 contact the gate electrodes 110a and 110b. Metal interconnections 116 are formed over the inter-layer insulator 114 and the contact plugs 115. The metal interconnections 116 contact the contact plugs 115 so that the metal interconnections 116 are electrically connected through the contact plugs 115 to the n-type source and drain regions 112a and 112c and the p-type source and drain regions 112b and 112d as well as to the gate electrodes 100a and 100b. A passivation film 117 is formed over the metal interconnections 116 and the inter-layer insulator 114, thereby completing a semiconductor device having a CMOS circuit.
Japanese Unexamined Patent Application, First Publication, No. 2-265248 discloses the source and drain regions having the lightly doped drain structure that can solve the problems that scaling down of the transistors causes field concentration near the drain thereby generating hot carriers and varying the threshold of the transistor.
As described above, the above-described conventional semiconductor device having the CMOS circuit includes the n-MOS transistor having the second gate insulating film 106 and the p-MOS transistor having the first gate insulating film 103. The n-MOS transistor has the second gate insulating film 106 of the second thickness Tox(NMOS). The p-MOS transistor has the first gate insulating film of the first thickness Tox(PMOS). The first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS). Forming the first and second gate insulating films 106 and 103 that differ in thickness from each other would need the following additional processes. The first gate insulating film 103 is formed over the n-MOS transistor region 104a and the p-MOS transistor region 104b. The first resist pattern 105 is formed over the gate insulating film 103 by the lithography process. The first resist pattern 105 has an opening that is positioned in the n-MOS transistor region 104a. The first gate insulating film 103 is selectively removed from the n-MOS transistor region 104a by using the first resist pattern 105 as a mask, while leaving the first gate insulating film 103 in the p-MOS transistor region 104b. The second gate insulating film 106 is selectively formed on the n-MOS transistor region 104a. The above-described additional processes increase the number of processes for manufacturing the semiconductor device.
Taking into account only the countermeasure to the NBTI problem of the p-MOS transistor, it could be proposed that, without carrying out any additional lithography processes, a single gate insulating film with a larger uniform thickness is formed over the n-MOS transistor region 104a and the p-MOS transistor region 104b. The thick gate insulating film on the n-MOS transistor region 104a may excessively reduce the on-current of the n-MOS transistor.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or method of forming the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.